1. Field of the Invention
The present invention relates to an integrated reduced media independent interface, and more specifically, to an integrated reduced media independent interface for reducing pin count and related method.
2. Description of the Prior Art
In modern society, information flows acrossnetworks so that people can share information and technology. With the growing need for bandwidth, significant development is occurring in the area of high-speed networking. In the future, Ethernet will not only be used in local area networks (LANs) but also in wide area networks (WANs).
In the related specifications of Ethernet, the media independent interface for connecting a medium access control circuit (MAC circuit) and a physical circuit (PHY Circuit) is replaced by the reduced media independent interface (RMII). The specification of the reduced media independent interface (RMII) is the same as the specification of the media independent interface (MII), and these specifications are essentially according to IEEE 802.3 and IEEE 802.3u.
Comparing the reduced media independent interface (RMII) with the media independent interface according to the prior art, the most important improvement is that chip pin count is reduced. In the manufacture of chips and in packaging techniques, ping count influences cost. The greater the number of pins is, the higher the cost is. This means that the reduced media independent interface provides a good choice of interface count with the IEEE 802.3u specification. Please refer to FIG. 1. FIG. 1 is a schematic diagram of the reduced media independent interface (RMII). From the above, the reduced media independent interface (RMII) 10 is used for connecting a medium access control circuit (MAC circuit) 12 and a physical circuit 14 (PHY circuit). The reduced media independent interface can be separated into two parts by the transmission direction of signals and data: a transmitter 16 and a receiver 18. In the transmitter 16 the transmission direction of signals is from the medium access control circuit (MAC circuit) 12 to the physical circuit 14. In the receiver 18, the transmission direction of signals and data is from the physical circuit 18 to the medium access control circuit (MAC circuit) 12. The reduced media independent interface can be separated into a plurality of specialized interfaces. The interfaces in the transmitter 16 include a transmission data interface (TXD) and a transmission-enabling interface (TX_EN). The transmission data interface is used for transmitting data from the medium access control circuit (MAC circuit) 12 to the physical circuit (PHY circuit). In general, there are two transmission speeds: 10 Mb/s and 100 Nb/s. When the transmission-enabling interface (TX_EN) outputs a high voltage in an assert mode, the physical circuit 14 receives the data transmitted from the medium access control circuit (MAC circuit) 12 through the transmission data interface. In other words, when the transmission-enabling interface (TX_EN) is not in assert mode (ex: the transmission-enabling interface outputs a predetermined low-voltage signal), the physical circuit does not receive data from the medium access control circuit (MAC circuit) 12.
Please refer to FIG. 1. The receiver 18 of the reduced media independent interface (RMII) 10 includes a reference clock interface (REF_CLK), a receiving-enabling interface, an error-detecting interface (RX_ER) and a data receiving interface (RXD). The reference clock interface is used for providing a reference clock to the specialized interfaces of the reduced media independent interface 10 (RMII) that include the transmission data interface (TXD), the transmission-enabling interface (TX_EN), the receiving-enabling interface (CRS_DV), the error-detecting interface (RX_ER), and the data receiving interface (RXD). The reference clock is generated by the MAC circuit 12 or by an external source. Therefore, the detail interfaces of the reduced media independent interface 10 (RMII) operate synchronously according to the reference clock. Please refer to the FIG. 2. FIG. 2 is a time sequence diagram relating to the plurality of interfaces of the receiver 18 in the reduced media independent interface 10 (RMII). The data receiving interface (RXD) is used for transmitting data from the physical circuit 14 (PHY circuit) to the medium access control circuit (MAC circuit) 12. When the reduced media independent interface 10 (RMII) is in an idle mode (the receiving-enabling interface is at a predetermined low voltage), the medium access control circuit (MAC circuit) 12 rejects data from the physical circuit (PHY circuit) 14 through the data receiving interface. When the receiver 18 operates, the physical circuit (PHY circuit) 14 does not detect an invalid code or other error information and the physical circuit 14 (PHY circuit) does not detect data to be transmitted, the reduced media independent interface 10 (RMII) is not in the idle mode, the receiving-enabling interface is set to a predetermined high voltage, the error-detecting interface (RX_ER) is at a low voltage, the reduced media independent interface 10 (RMII) is in a transmission-enabling mode, and the medium access control circuit (MAC circuit) 12 receives data from the physical circuit 14 through the data receiving interface (RXD). When the physical circuit (PHY circuit) detects the invalid code or other error information, the error-detecting interface is in a predetermined high voltage and the medium access control circuit (MAC circuit) 12 detects data from the physical circuit 14 (PHY circuit) as invalid data. At this moment, the reduced media independent interface is in an error-detection mode, and the medium access control circuit (MAC circuit) 12 rejects data from the data receiving interface 14. So, the error-detecting interface (RX_ER) can improve the rate of transmission of correct data in the reduced media independent interface 10 (RMII).
However, in the requirement for reducing spin count and in consideration of conforming the specification of the reduced media independent interface 10 (RMII), when the prior art reduced media independent interface is designed adaptively, it is better to further reduce the pin count of the reduced media independent interface lower the cost of the related products.